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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
November 2002
ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
General Description
The ACE8001 is a member of the ACEx (Arithmetic Controller Engine) family of microcontrollers. It is a dedicated programmable monolithic integrated circuit for applications requiring high performance, low power, and small size. It is a fully static part fabricated using CMOS technology. The ACE8001 product family has an 8-bit core processor, 64 bytes of RAM, 64 bytes of data EEPROM and 1K bytes of code EEPROM. Its on-chip peripherals include a programmable 8-bit timer with PWM output, watch-dog/idle timer, and programmable undervoltage detection circuitry. The on-chip clock and reset functions reduce the number of required external components. The ACE8001 product family is available in 8-pin SOIC and TSSOP packages. s Multi-input wake-up 3 I/O pins s 8-bit Timer1 with PWM output s On-chip oscillator -- No external components -- 1s instruction cycle time s On-chip Power-on Reset -- External Reset pin option (ACE8000) s Brown-out Reset s Programmable read and write disable functions s Memory mapped I/O s Multilevel Low Voltage Detection s Fully static CMOS -- Low power HALT mode (100nA @ 3.3V) -- Power saving IDLE mode s Single supply operaton -- 2.2 - 5.5V s Software selectable I/O options -- Push-pull outputs with tri-state option -- Weak pull-up or high impedance inputs s 40 years data retention s 1,000,000 writes s 8-pin SOIC and TSSOP packages.
Features
s s s s s s Arithmetic Controller Engine 1K bytes on-board code EEPROM 64 bytes data EEPROM Fast Startup (<10S) 64 bytes RAM Watchdog
Block and Connection Diagram
VCC1 GND1 RESET (CKO) G0 (CKI) G1 (T1) G2 (MIW) G3 2 (MIW) G4 (MIW) G5
1. 100nf decoupling capacitor recommended. 2. Input only
Power-on Reset
Brown-out Reset
Internal Oscillator
HALT & IDLE Power Saving Modes 12-bit Timer0 with Watchdog Timer
GPORT general purpose I/O with multiinput wakeup on 3 inputs
ACE1001 core (4 interrupt sources and vectors)
8-bit PWM Timer1
Programming Interface
64 bytes of Data EEPROM
1K bytes of Code EEPROM
64 bytes of RAM
(c)2002 Fairchild Semiconductor Corporation
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
Figure 1: ACE8001 SOIC 8-Pin Device Pinout (a) Normal Operation
(b) Programming Mode
(MIW) G3 (MIW) G4 (MIW) G5 (CKO) G0
1 2 3 4
8 7 6 5
VCC GND G2 (T1) G1 (CKI)
LOAD SFT_IN NC/VCC NC
1 2 3 4
8 7 6 5
VCC GND SFT_OUT CKI
Figure 2: ACE8000 SOIC 8-Pin Reset Option (a) Normal Operation
(b) Programming Mode
(MIW) G3 (MIW) G4 Reset (CKO) G0
1 2 3 4
8 7 6 5
VCC GND G2 (T1) G1 (CKI)
LOAD SFT_IN NC NC
1 2 3 4
8 7 6 5
VCC GND SFT_OUT CKI
Figure 3: ACE8001 TSSOP 8-Pin Device Pinout (a) Normal Operation
(b) Programming Mode
VCC (MIW) G3 (MIW) G5 (MIW) G4
1 2 3 4
8 7 6 5
G2 (T1) GND G1 (CKI) G0 (CKO)
VCC LOAD NC/VCC SFT_IN
1 2 3 4
8 7 6 5
SFT_OUT GND CKI NC
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
2.0 Electrical Characteristics Absolute Maximum Ratings
Ambient Storage Temperature Input Voltage not including G3 G3 Input Voltage Lead Temperature (10s max) Electrostatic Discharge on all pins -65C to +150C -0.3V to VCC+0.3V 0.3V to 13V +300C 2000V min
Operating Conditions
Relative Humidity (non-condensing) EEPROM write limits 95% See DC Electrical Characteristics
Device
ACE8001 ACE8001E ACE8000 ACE8000E
Operating Voltage
2.2 to 5.5V 2.2 to 5.5V 2.2 to 5.5V 2.2 to 5.5V
Operating Temperature
0C to 70C -40C to +85C 0C to 70C -40C to +85C
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
ACE8001 DC Electrical Characteristics
VCC = 2.2 to 5.5V All measurements valid for ambient operating temperature unless otherwise stated. Symbol
ICC
3
Parameter
Supply Current - no data EEPROM write in progress
Conditions
-40C to +85C 2.2V 2.7V 3.3V 5.5V 3.3V @ -40C to +85C 5.5V @ -40C to +85C
MIN
TYP
0.4 0.7 1.2 3.7 100 0.7 120 140
MAX
1.0 1.2 2.0 6.0 5000 25 200 350 5.5 5.5 10ms/V 0.2VCC
Units
mA mA mA mA nA A A A V V
ICCH ICCL4 VCCW
HALT Mode current
IDLE Mode Current EEPROM Write Voltage
3.3V 5.5V Code EEPROM in Programming Mode Data EEPROM in Operating Mode 4.5 2.4 1s/V VCC = 2.2 -5.5V VCC = 2.2V VCC > 2.2V VCC =5.5V, VIN =0V VCC =5.5V VCC = 2.2V - 3.3V 3.0 mA sink 5.0 mA sink VCC = 3.3V - 5.5V 5.0 mA sink 10.0 mA sink VCC = 2.2V - 5.5V 0.4 mA source 0.8 mA source VCC = 3.3V - 5.5V 0.4 mA source 1.0 mA source 0.8VCC 0.8VCC 0.8VCC 0.8VCC 0.9VCC 0.8VCC 30
5.0
SVCC VIL VIH IIP ITL VOL
Power Supply Slope Input Low with Schmitt Trigger Buffer Input High with Schmitt Trigger Buffer Input Pull-up Current TRI-STATE Leakage Output Low Voltage G0, G1, G2, G4 G5 Output Low Voltage G0, G1, G2, G4 G5
V V V
65 2
350 200
A nA
0.2VCC 0.2VCC 0.2VCC 0.2VCC
V V
V V
VOH
Output High Voltage G0, G1, G2, G4 G5 Output High Voltage G0, G1, G2, G4 G5
V V
V V
3 4
ICC active current is dependent on the program code. Based on a continuous IDLE looping program.
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
ACE8001 AC Electrical Characteristics
VCC = 2.2 to 5.5V All measurements valid for ambient operating temperature unless otherwise stated. Parameter
Instruction cycle time from internal clock - setpoint Internal clock frequency variation
Conditions
5.0V at +25C 2.4V to 5.5V at constant temperature 2.4V to 5.5V at full temperature range
MIN
0.96
TYP
1.0
MAX
1.04 10
Units
s % % MHz MHz ms s cycles
-12
+8 4 4 2.5 3 20 5
Crystal oscillator frequency External clock frequency EEPROM write time Internal clock start up time Oscillator start up time
5 The 6 The
(Note 5) (Note 5)
(Note 6) (Note 6)
maximum permissible frequency is guaranteed by design but not 100% tested. parameter is guaranteed by design but not 100% tested.
ACE8001 Electrical Characteristics for programming
All data following is valid between 4.5V and 5.5V at ambient temperature. The following characteristics are guaranteed by design but are not 100% tested. See "EEPROM write time" in the AC Electrical Characteristics for definition of the programming ready time. Parameter
tHI tLO tDIS tDIH tDOS tDOH tSV1, tSV2 tLOAD1, tLOAD2, tLOAD3, tLOAD4 VSUPERVOLTAGE
Description
CLOCK high time CLOCK low time SHIFT_IN setup time SHIFT_IN hold time SHIFT_OUT setup time SHIFT_OUT hold time LOAD supervoltage timing LOAD timing Supervoltage level
MIN
500 500 100 100 100 900 50 5 11.5
MAX
DC DC
Units
ns ns ns ns ns ns s s
12.5
V
ACE8001 Brown-out Reset (BOR) Characteristics
VCC = 2.2 to 5.5V Parameter
BOR Voltage Threshold Variation (BLSEL = 1)
Conditions
-40C to +85C
MIN
TYP
2.25
MAX
Units
V
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
3.0 AC & DC Electrical Characteristic Graphs
The graphs in this section are for design guidance and are based on preliminary test data. Figure 4: RC Oscillator Frequency vs. Temperature
(a) VCC = 5.0V
2.600 2.400 2.200 2.000 1.800 1.600 1.400 1.200 1.000 3.3k/82pF 5.6k/100pF 6.8K/100pF
Frequency (MHz)
Avg Min Max
Resistor & Capacitor Values [k & pF] (b)VCC=2.5V
1.600
Frequency (MHz)
1.400 1.200 1.000 0.800 0.600 3.3k/82pF 5.6k/100pF 6.8K/100pF
Avg Min Max
Resistor & Capacitor Values [k & pF]
Figure 5: Internal Oscillator Frequency
1.040
1.020
1.000
Frequency (MHz)
0.980
0.960
0.940
2.4 V 3.0 V 3.3 V 3.6 V 4.0 V 4.5 V 5.0 V 5.5 V
0.920
0.900
0.880 -45C -20C 0C 25C 85C 125C
Temperature (C)
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
Figure 6: LBD and BOR Threshold Levels LBD Voltage Levels vs. Temperature
4.00
3.80
3.60
3.40
Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8
Voltage (V)
3.20
3.00
2.80
2.60
2.40
2.20
2.00 -45C 0C 25C 85C 125C
Temperature [C]
BOR Voltage Level vs. Temperature
2.70
2.60
2.50
2.40
Voltage (V)
2.30
BOR Level
2.20
2.10
2.00
1.90 -45C 0C 25C 85C 125C
Temperature [C]
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
Figure 7: ICC Active Current ICC Active (no data EEPROM writes) vs. Temperature
4.50
4.00
3.50
3.00
Current (mA)
2.50
2.00
2.2V 2.7V 3.3V 5.0V 5.5V
1.50
1.00
0.50
0.00 -45 0 25 85 125
Temperature [C]
ICC Active (data EEPROM writes) vs. Temperature
12.00
10.00
8.00
Current (mA)
6.00
2.2V 2.7V 3.3V 5.0V 5.5V
4.00
2.00
0.00 -45 0 25 85 125
Temperature [C]
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
Figure 8: HALT Mode Currents HALT current vs. Temperature
12.000
10.000
8.000
Current (nA)
6.000
5.5V 5.0V 3.3V
4.000
2.000
0.000 -45C 0C 25C 85C 125C
Temperature [C]
Figure 9: IDLE Mode Current
IDLE current vs. Temperature
160.00
140.00
120.00
100.00
Current (A)
80.00
2.2V 2.7V 3.3V 5.0V 5.5V
60.00
40.00
20.00
0.00 -45 0 25 85 125
Temperature [C]
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
Figure 10: VOL/VOH
VOL vs. IOL (G5 @ 25C)
0.80 0.70 0.60 1.40 1.20 1.00
VOL vs. IOL (G0-G4 @ 25C)
Voltage (V)
0.50 0.40 0.30 0.20 0.10 0.00 0 2 5 8 15
2.2V 2.7V
Voltage (V)
0.80 0.60 0.40 0.20 0.00 0 2 5 8 15
2.2V 2.7V 3.3V 3.6V 5.5V
Current (mA)
Current (mA)
VOH vs. IOH (G0-G4 @ 25C)
6.00 5.50 5.00 4.50 6.00 5.50 5.00 4.50
VOH vs. IOH (G5 @ 25C)
Voltage (V)
4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 0.2 0.4 0.5 0.8 1 1.2
2.2V 2.7V
4.00 3.50 3.00 2.50 2.00 1.50 1.00 0 0.2 0.4 0.5 0.8 1 1.2
2.2V 2.7V 3.3V 3.6V 5.5V
Current (mA)
Current (mA)
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
4.0 Arithmetic Controller Core
The ACEx microcontroller core is specifically designed for low cost applications involving bit manipulation, shifting and arithmetic operations. It is based on a modified Harvard architecture meaning peripheral, I/O, and RAM locations are addressed separately from instruction data. The core differs from the traditional Harvard architecture by aligning the data and instruction memory sequentially. This allows the X-pointer (11-bits) to point to any memory location in
either segment of the memory map. This modification improves the overall code efficiency of the core and takes advantage of the flexibility found on Von Neumann style machines.
4.1 CPU Registers
The ACEx microcontroller has five general-purpose registers. These registers are the Accumulator (A), X-Pointer (X), Program Counter (PC), Stack Pointer (SP), and Status Register (SR). The X, SP, and SR registers are all memory-mapped.
Figure 11: Programming Model
A X PC SP SR 10 9
7
0 0 0 3 0
8-bit accumulator register 11-bit X pointer register 10-bit program counter 4-bit stack pointer 8-bit status register NEGATIVE flag HALF CARRY flag (from bit 3) CARRY flag (from MSB) ZERO flag GLOBAL Interrupt Mask READY flag (from EEPROM)
R 0 0GZCHN
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
4.1.1 Accumulator (A)
The Accumulator is a general-purpose 8-bit register that is used to hold data and results of arithmetic calculations or data manipulations.
4.1.2 X-Pointer (X)
The X-Pointer register allows for an 11-bit indexing value to be added to an 8-bit offset creating an effective address used for reading and writing between the entire memory space. (Software can only read from code EEPROM.) This provides software with the flexibility of storing lookup tables in the code EEPROM memory space for the core's accessibility during normal operation. The X register is divided into two sections. The 10 least significant bits (LSB) of the register is the address of the program or data memory space. The most significant bit (MSB) of the register is write only and selects between the data (0x000 to 0x0FF) or program (0xC00 to 0xFFF) memory space. Example: If Bit 10 = 0, then the LD A, [00,X] instruction will take a value from address range 0x000 to 0x0FF and load it into A. If Bit 10 = 1, then the LD A, [00,X] instruction will take a value from address range 0xC00 to 0xFFF and load it into A.
The stack is configured as a data structure which decrements from high to low memory. Each time a new address is pushed onto the stack, the core decrements the stack pointer by two. Each time an address is pulled from the stack, the core increments the stack pointer by two. At any given time, the stack pointer points to the next free location in the stack. When a subroutine is called by a jump to subroutine (JSR) instruction, the address of the instruction is automatically pushed onto the stack least significant byte first. When the subroutine is finished, a return from subroutine (RET) instruction is executed. The RET instruction pulls the previously stacked return address from the stack and loads it into the program counter. Execution then continues at the recovered return address.
4.1.5 Status Register (SR)
This 8-bit register contains four condition code indicators (C, H, Z, and N), an interrupt masking bit (G), and an EEPROM write flag (R). The condition code indicators are automatically updated by most instructions. (See Table 8)
Carry/Borrow (C)
The carry flag is set if the arithmetic logic unit (ALU) performs a carry or borrow during an arithmetic operation and by its dedicated instructions. The rotate instruction operates with and through the carry bit to facilitate multiple-word shift operations. The LDC and INVC instructions facilitate direct bit manipulation using the carry flag.
4.1.3 Program Counter (PC)
The 10-bit program counter register contains the address of the next instruction to be executed. After a reset, if in normal mode the program counter is initialized to 0xC00.
4.1.4 Stack Pointer (SP)
The ACEx microcontroller has an automatic program stack with a 4-bit stack pointer. The stack can be initialized to any location between addresses 0x30-0x3F. After a reset, the stack pointer is defaulted to 0xF pointing to address 0x3F. Normally, the stack pointer is initialized by one of the first instructions in an application program.
Half Carry (H)
The half carry flag indicates whether an overflow has taken place on the boundary between the two nibbles in the accumulator. It is primarily used for Binary Coded Decimal (BCD) arithmetic calculation.
Zero (Z)
The zero flag is set if the result of an arithmetic, logic, or data manipulation operation is zero. Otherwise, it is cleared.
Figure 12: Basic Interrupt Structure
Interrupt Source with Priority
INTR T1 T0 MIW
T1PND
T0PND
Interrupt
WKPND
Interrupt Pending Flags
T1EN
T0INT EN
WKINT EN
G
Interrupt Enable Bits
Global Interrupt Enable
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
Negative (N)
The negative flag is set if the MSB of the result from an arithmetic, logic, or data manipulation operation is set to one. Otherwise, the flag is cleared. A result is said to be negative if its MSB is a one.
stacked and the G bit is cleared. This means, if the G bit was enabled prior to the software interrupt the RETI instruction must be used to return from interrupt in order to restore the G bit to its previous state. However, if the G bit was not enabled prior to the software interrupt the RET instruction must be used. In case of multiple interrupts occurring at the same time, the ACEx microcontroller core has prioritized the interrupts. The interrupt priority sequence in shown in Table 6.
Interrupt Mask (G)
The interrupt request mask (G) is a global mask that disables all maskable interrupt sources. If the G Bit is cleared, interrupts can become pending, but the operation of the core continues uninterrupted. However, if the G Bit is set an interrupt is recognized. After any reset, the G bit is cleared by default and can only be set by a software instruction. When an interrupt is recognized, the G bit is cleared after the PC is stacked and the interrupt vector is fetched. Once the interrupt is serviced, a return from interrupt instruction is normally executed to restore the PC to the value that was present before the interrupt occurred. The G bit is the reset to one after a return from interrupt is executed. Although the G bit can be set within an interrupt service routine, "nesting" interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism.
4.3 Addressing Modes
The ACEx microcontroller has six addressing modes indexed, direct, immediate, absolute jump, and relative jump.
Indexed
The instruction allows an 8-bit unsigned offset value to be added to the 10-LSBs of the X-pointer yielding a new effective address. This mode can be used to address any memory space (program or data).
Direct
The instruction contains an 8-bit address field that directly points to the data memory space as an operand.
4.2 Interrupt handling
When an interrupt is recognized, the current instruction completes its execution. The return address (the current value in the program counter) is pushed onto the stack and execution continues at the address specified by the unique interrupt vector (see Table 9). This process takes five instruction cycles. At the end of the interrupt service routine, a return from interrupt (RETI) instruction is executed. The RETI instruction causes the saved address to be pulled off the stack in reverse order. The G bit is set and instruction execution resumes at the return address. The ACEx microcontroller is capable of supporting four interrupts. Three are maskable through the G bit of the SR and the fourth (software interrupt) is not inhibited by the G bit (see Figure 12). The software interrupt is generated by the execution of the INTR instruction. Once the INTR instruction is executed, the ACEx core will interrupt whether the G bit is set or not. The INTR interrupt is executed in the same manner as the other maskable interrupts where the program counter register is
Immediate
The instruction contains an 8-bit immediate field as an operand.
Inherent
This instruction has no operands associated with it.
Absolute
The instruction contains a 10-bit address that directly points to a location in the program memory space. There are two operands associated with this addressing mode. Each operand contains a byte of an address. This mode is used only for the long jump (JMP) and JSR instructions.
Relative
This mode is used for the short jump (JP) instructions where the operand is a value relative to the current PC address. With this instruction, software is limited to the number of bytes it can jump, -31 or +32.
Table 6: Interrupt Priority Sequence Priority (4 highest, 1 lowest)
4 3 2 1
Interrupt
MIW (EDGEI) Timer0 (TMRI0) Timer1 (TMRI1) Software (INTR)
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
Table 7: Instruction Addressing Modes Instruction
ADC AND SUBC XOR CLR INC DEC IFEQ IFGT IFNE SC RC IFC IFNC INVC LDC STC RLC RRC LD ST LD NOP IFBIT SBIT RBIT JP JSR JMP RET RETI INTR #, M #, M #, M Rel M M no-op no-op no-op A, # M, # X, # A, M A, M M, M A, [00,X] A, [00,X] no-op A, # A, # A, # M,#
Immediate
A, # A, # A, # A, #
Direct
A, M A, M A, M A, M M M M A, M A, M A, M
Indexed
Inherent
Relative
Absolute
A A A
X X
no-op no-op no-op no-op no-op #, M #, M A A
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
Table 8: Instruction Cycles and Bytes
Mnemonic
ADC ADC AND AND CLR CLR DEC DEC DEC IFBIT IFC IFEQ IFEQ IFEQ IFGT IFGT IFNE IFNE IFNC INC INC INC INTR INVC JMP M A M X A, # A, M M, # A, # A, M A, # A, M
Operand
A, # A, M A, # A, M A M A M X #, M
Bytes
2 2 2 2 1 2 1 2 1 2 1 2 2 3 2 2 2 2 1 1 2 1 1 1 3
Cycles
2 2 2 2 1 1 1 2 1 2 1 2 2 3 2 2 2 2 1 1 2 1 5 1 4
Flags affected
C,H,Z,N C,H,Z,N Z,N Z,N Z,N,C,H Z,N,C,H Z,N Z,N Z None None None None None None None None None None Z,N Z,N Z None C None
Mnemonic
JP JSR LD LD LD LD LD LD LDC NOP RBIT RC RET RETI RLC RRC SBIT SC ST ST STC SUBC SUBC XOR XOR
Operand
M A, # A, [00,X] A, M M, # M, M X, # #, M
Bytes
1 3 2 2 2 3 3 3 2 1
Cycles
1 5 2 3 2 3 3 3 2 1 2 1 5 5 1 1 2 1 3 2 2 2 2 2 2
Flags affected
None None None None None None None None C None Z,N C,H None None C,Z,N C,Z,N Z,N C,H None None Z,N C,H,Z,N C,H,Z,N Z,N Z,N
#, M
2 1 1 1
A A #, M
1 1 2 1
A, [00,X] A, M #, M A, # A, M A, # A, M
2 2 2 2 2 2 2
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
4.4 Memory Map
All I/O ports, peripheral registers and core registers (except the accumulator and the program counter) are mapped into memory space.
Table 9: Memory Map Address
0x00 - 0x3F 0x40 - 0x7F 0xAA 0xAB, 0xAD 0xAC 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 - 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xCE 0xCF 0xC00 - 0xFF5 0xFF6 - 0xFF7 0xFF8 - 0xFF9 0xFFA - 0xFFB 0xFFC - 0xFFD 0xFFE - 0xFFF Data Data Data Data Data Data Data Data Program Program Program Program Program Init. Reg. Init. Reg. LBD Core Core Clock Core Core EEPROM Core Core Core Core Data Data Data Data Data Data Data Data Data Data Data Timer1 Timer1 MIW MIW MIW I/O I/O I/O Timer0 Timer0 Clock
Memory Space
Data Data Data
Block
SRAM EEPROM Timer1 Data RAM
Contents
Data EEPROM T1RA register Reserved TMR1 register T1CNTRL register WKEDG register WKPND register WKEN register PORTGD register PORTGC register PORTGP register WDSVR register T0CNTRL register HALT mode register Reserved Initialization register 1 Initialization register 2 LBD register XHI register XLO register Power mode clear (PMC) register SP register Status register (SR) Code EEPROM Timer0 Interrupt vector Timer1 Interrupt vector MIW Interrupt vector Soft Interrupt vector Reserved
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
4.5 Memory
The ACEx microcontroller device has 64 bytes of SRAM and 64 bytes of EEPROM available for data storage. The device also has 1K bytes of EEPROM for program storage. Software can read and write to SRAM and data EEPROM but can only read from the code EEPROM. While in normal mode, the code EEPROM is protected from any writes. The code EEPROM can only be rewritten when the device is in program mode and if the write disable (WDIS) bit of the initialization register is not set to 1. While in normal mode, the user can write to the data EEPROM array by 1) polling the ready (R) flag of the SR, then 2) executing the appropriate instruction. If the R flag is 1, the data EEPROM block is ready to perform the next write. If the R flag is 0, the data EEPROM is busy. The data EEPROM array will reset the R flag after the completion of a write cycle. Attempts to read, write, or enter HALT/IDLE mode while the data EEPROM is busy (R = 0) can affect the current data being written.
4.6 Initialization Registers
The ACEx microcontroller has two 8-bit wide initialization registers. These registers are read from the memory space on power-up to initialize certain on-chip peripherals. Figure 13 provides a detailed description of Initialization Register 1. The Initialization Register 2 is used to trim the internal oscillator to its appropriate frequency. This register is pre-programmed in the factory to yield an internal instruction clock of 1MHz. Both Initialization Registers 1 and 2 can be read from and written to during programming mode. However, re-trimming the internal oscillator (writing to the Initialization Register 2) once it has left the factory is discouraged.
Figure 13: Initialization Register 1 Bit 7
(0) RDIS 8,9 (1) WDIS 8,9 (2) UBD 8,9 (3) BLSEL 7 (4) BOREN (5) WDEN (6) CMODE[1] (7) CMODE[0]
7 The 8 If 9 If
Bit 6
Bit 5
WDEN
Bit 4
BOREN
Bit 3
BLSEL
7
Bit 2
UBD
8,9
Bit 1
WDIS
8,9
Bit 0
RDIS 8,9
CMODE[0:1]
If set, disables attempts to read the contents from the EEPROMs while in programming mode If set, disables attempts to write new contents to the EEPROMs while in programming mode If set, the device will not allow any writes to occur in the upper block of data EEPROM (0x60-0x7F) If set, the Brown-out Reset (BOR) voltage reference level is set to its higher range for the ACE8001 If not set, the BOR voltage reference level is set to its lower range If set, allows a BOR to occur if VCC falls below the voltage reference level If set, enables the on-chip processor watchdog circuit Clock mode select bit 1 (See table 13) Clock mode select bit 0 (See table 13)
BLSEL bit is set to its appropriate level in the factory. If writing to the initialization register is necessary, be sure to maintain bits set value.
both the WDIS and RDIS bits are set, the device will no longer be able to be placed into program mode. the RDIS or UBD bits are not set while the WDIS bit is not set, then the RDIS and UBD bits can be reset.
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5.0 Timer 1
Timer 1 is a versatile 8-bit timer. Its main function is to operate as a Pulse Width Modulation (PWM) generator that generates pulses of a specified width and duty cycles. Timer 1 contains an 8-bit timer register (TMR1), an 8-bit autoreload register (T1RA), and an 8-bit control register (T1CNTRL). All registers are memory-mapped for simple access through the core. For the PWM signal generation the timer contains an output (T1) that is multiplexed with the I/O pin G2. The timer can be started or stopped through the T1CNTRL register bit T1C0. When running, the timer counts down (decrements) every clock cycle. The timer's clock has a pre-scalar and is selectable through two T1CNTRL register bits T1PSC[1:0]. Depending on the selected operating mode, occurrences of
timer underflow (transitions from 0x00 to 0xFF or reload) can either generate an interrupt and/or toggle the T1 output pin. Timer 1's interrupt (TMRI1) can be enabled by the interrupt enable (T1EN) bit in the T1CNTRL register. When the timer interrupt is enabled, the source of the interrupt is a timer underflow. By default, the timer register is reset to 0xFF and the autoreload register is reset to 0x00.
5.1 Timer control bits
Reading and writing to the T1CNTRL register controls the timer's operation. By writing to the control bits, the user can enable or disable the timer interrupts, set the mode of operation, start or stop the timer, and select the clock. The T1CNTRL register bits are described in Table 10.
Table 10: TIMER1 Control Register Bits T1CNTRL Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1,0
Name
--------------------T1C1 T1C0 T1PND T1EN T1PSC Reserved Reserved
Function
T1 toggle enable bit: 1 = T1 toggle enabled, 0 = T1 toggle disabled TMR1 run: 1 = Start timer, 0 = Stop timer Timer1 interrupt pending flag: 1 = Timer1 interrupt pending, 0 = Timer1 interrupt not pending Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled, 0 = Timer1 interrupt disabled Pre-scalar selection bits: Selects the 1MHz clock divider to be by 1 (00b), 2 (01b), 4 (10b), or 8 (11b)
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5.2 Pulse Width Modulation (PWM) Mode
In the PWM mode, the timer counts down at the instruction clock rate. When an underflow occurs, the timer register is reloaded from T1RA and the count down proceeds from the loaded value. At every underflow, a pending flag (T1PND) located in the T1CNTRL register is set. Software must then clear the T1PND flag and load the T1RA register with an alternate PWM value. In addition, the timer can be configured to toggle the T1 output bit upon underflow. Configuring the timer to toggle T1 results in the generation of a signal outputted from port G2 with the width and duty cycle controlled by the values stored in the T1RA. A block diagram of the timer's PWM mode of operation is shown in Figure 14. The timer has one interrupt (TMRI1) that is maskable through the T1EN bit of the T1CNTRL register. However, the core is only interrupted if the T1EN bit and the G (Global Interrupt enable) bit of the SR is set. If interrupts are enabled, the timer will generate an interrupt each time T1PND flags is set (whenever the timer underflows provided that the pending flag was cleared.) The interrupt service routine is responsible for proper handling of the T1PND flag and the T1EN bit. The interrupt will be synchronous with every rising and falling edge of the T1 output signal. Generating interrupts only on rising or falling edges of T1 is achievable through appropriate handling of the T1EN bit or T1PND flag through software. The following steps show how to properly configure Timer 1 to operate in the PWM mode. For this example, the T1 output signal is toggled with every timer underflow and the "high" and "low" times for the T1 output can be set to different values. The T1 output signal can start out either high or low depending on the configuration of I/O G2; the instructions below are for starting with the T1 output high. Follow the instructions in parentheses to start the T1 output low.
1. Configure T1 as an output by setting bit 2 of PORTGC. - SBIT 2, PORTGC ; Configure G2 as an output 2. Initialize T1 to 1 (or 0) by setting (or clearing) bit 2 of PORTGD. - SBIT 2, PORTGD ; Set G2 high 3. Load the initial PWM high (low) time into the timer register. - LD TMR1, #6FH ; High (Low) for .444ms (1MHz/4 clock) 4. Load the PWM low (high) time into the T1RA register. - LD T1RA, #2FH ; Low (High) for .188ms (1MHz/4 clock) 5. Write the appropriate control value to the T1CNTRL register to select PWM mode with T1 toggle, to select the divide by 4 pre-scalar, and to clear the enable and pending flags. (See Table 12) - LD T1CNTRL, #22H ; Setting the T1C0 bit starts the timer 6. Set the T1CO bit to start the timer. - SBIT T1CP, T1CNTRL ; T1CO equals 4 7. After every underflow, load T1RA with alternate values. If the user wishes to generate an interrupt on timer output transitions, reset the pending flags and then enable the interrupt using T1EN. The G bit must also be set. The interrupt service routine must reset the pending flag and perform whatever processing is desired. - RBIT T1PND, T1CNTRL ; T1PND equals 3 - LD T1RA, #6FH ; Low for .444ms (1MHz/4 clock)
Figure 14: Pulse Width Modulation Mode Underflow Interrupt T1 Instruction Clock
/8 /4 /2 3 2 1 0
Sel
8-bit Auto-Reload Register (T1RA) Data Latch Data Bus
8-bit Timer (TMR1)
T1PSC[1:0]
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6.0 Timer 0
Timer 0 is a 12-bit free running idle timer. Upon power-up or any reset, the timer is reset to 0x000 and then counts up continuously based on the instruction clock of 1MHz (1 s). Software cannot read from or write to this timer. However, software can monitor the timer's pending (T0PND) bit that is set every 8192 cycles (initially 4096 cycles after a reset or after the watchdog has been- serviced). The T0PND flag is set every other time the timer overflows (transitions from 0xFFF to 0x000). After an overflow, the timer will reset and restart its counting sequence. Software can either poll the T0PND bit or vector to an interrupt subroutine. In order to interrupt on a T0PND, software must be sure to enable the Timer 0 interrupt enable (T0INTEN) bit in the Timer 0 control (T0CNTRL) register and also make sure the G bit is set in SR. Once the timer interrupt is serviced, software should reset the T0PND bit before exiting the routine. Timer 0 supports the following functions: 1. Exiting from IDLE mode (See Section 16.0 for details.) 2. Start up delay from HALT mode 3. Watchdog pre-scalar (See Section 7.0 for details.) The T0INTEN bit is a read/write bit. If set to 0, interrupt requests from the Timer 0 are ignored. If set to 1, interrupt requests are accepted. Upon reset, the T0INTEN bit is reset to 0. The T0PND bit is a read/write bit. If set to 1, it indicates that a Timer 0 interrupt is pending. This bit is set by a Timer 0 overflow and is reset by software or system reset.
The WKINTEN bit is used in the Multi-input Wakeup/Interrupt block. See Section 8.0 for details.
7.0 Watchdog
The Watchdog timer is used to reset the device and safely recover in the rare event of a processor "runaway condition." The 12-bit Timer 0 is used as a pre-scalar for Watchdog timer. The Watchdog timer must be serviced before every 61,440 cycles but no sooner than 4096 cycles since the last Watchdog reset. The Watchdog is serviced through software by writing the value 0x1B to the Watchdog Service (WDSVR) register (see Figure 16). The part resets automatically if the Watchdog is serviced too frequent, or not frequent enough. The Watchdog timer must be enabled through the Watchdog enable bit (WDEN) in the initialization register. The WDEN bit can only be set while the device is in programming mode. Once set, the Watchdog will always be powered-up enabled. Software cannot disable the Watchdog. The Watchdog timer can only be disabled in programming mode by resetting the WDEN bit as long as the memory write protect (WDIS) feature is not enabled.
WARNING
Ensure that the Watchdog timer has been serviced before entering IDLE mode because it remains operational during this time.
Figure 15: Timer 0 Control Register Definition (T0CNTRL) Bit 7
WKINTEN
Bit 6
x
Bit 5
x
Bit 4
x
Bit 3
x
Bit 2
x
Bit 1
T0PND
Bit 0
T0EN
Figure 16: Watchdog Server Register (WDSVR) Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
0
Bit 1
1
Bit 0
1
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8.0 Multi-Input Wakeup/Interrupt Block
The Multi-Input Wakeup (MIW)/Interrupt contains three memory-mapped registers associated with this circuit: WKEDG (Wakeup Edge), WKEN (Wakeup Enable), and WKPND (Wakeup Pending). Each register has three bits with each bit corresponding to an input pins as shown in Figure 17. All three registers are initialized to zero upon reset. The WKEDG register establishes the edge sensitivity for each of the wake-up input pin: either (0) rising edge or (1) falling edge. The WKEN register enables (1) or disables (0) each of the port pins for the Wakeup/Interrupt function. The wakeup I/Os used for the Wakeup/Interrupt function must also be configured as an input pin in its associated port configuration register. However, an interrupt (EDGE1) of the core will not occur unless interrupts are enabled for the block via bit 7 of the T0CNTRL register (see Figure 15) and the G (global interrupt enable) bit of the SR is set. The WKPND register contains the pending flags corresponding to each of the port pins (1 for wakeup/interrupt pending, 0 for wakeup/interrupt not pending). To use the Multi-Input Wakeup/Interrupt circuit, perform the steps listed below. Performing the steps in the order shown will prevent false triggering of a Wakeup/Interrupt condition. This same procedure should be used following any type of reset because the wakeup inputs are left floating after resets resulting in unknown data on the port inputs. 1. Clear the WKEN register. -CLR WKEN 2. If necessary, write to the port configuration register to select the desired port pins to be configured as inputs. -RBIT 4, PORTGC ;G3, G4, and/or G5 3. If necessary, write to the port data register to select the desired port pins input state. -SBIT 4, PORTGD ;Pull-up 4. Write the WKEDG register to select the desired type of edge sensitivity for each of the pins used. -LD WKEDG, #38H ;Falling edges 5. Clear the WKPND register to cancel any pending bits. -CLR WKPND
6. Set the WKEN bits associated with the pins to be used, thus enabling those pins for the Wakeup/Interrupt function. -LD WKEN, #38H ;Enabling G3, G4, G5 Once the Multi-Input Wakeup/Interrupt function has been configured, a transition sensed on any of the enabled pins will set the corresponding bit in the WKPND register. The WKPND bits can bring the device out of the HALT/IDLE mode and can also trigger an interrupt if the interrupt is enabled. The interrupt service routine can read the WKPND register to determine which pin sensed the interrupt. The interrupt service routine or other software should clear the pending bit. The device will not enter HALT/IDLE mode as long as a WKPND pending bit is pending and enabled. The user has the responsibility of clearing the pending flags before attempting to enter the HALT/IDLE mode. Upon reset, the WKEDG register is configured to select positivegoing edge sensitivity for all wakeup inputs. If the user wishes to change the edge sensitivity of a port pin, use the following procedure to avoid false triggering of a Wakeup/Interrupt condition. 1. Clear the WKEN bit associated with the pin to disable that pin. 2. Write the WKEDG register to select the new type of edge sensitivity for the pin. 3. Clear the WKPND bit associated with the pin. 4. Set the WKEN bit associated with the pin to re-enable it. PORTG provides the user with three fully selectable, edge sensitive interrupts that are all vectored into the same service subroutine. The interrupt from PORTG shares logic with the wakeup circuitry. The WKEN register allows interrupts from PORTG to be individually enabled or disabled. The WKEDG register specifies the trigger condition to be either a positive or a negative edge. The WKPND register latches in the pending trigger conditions. Since PORTG is also used for exiting the device from the HALT/ IDLE mode, the user can elect to exit the HALT/IDLE mode either with or without the interrupt enabled. If the user elects to disable the interrupt, then the device restarts execution from the point at which it was stopped (first instruction cycle of the instruction following HALT/IDLE mode entrance instruction). In the other case, the device finishes the instruction that was being executed when the part was stopped and then branches to the interrupt service routine. The device then reverts to normal operation.
Figure 17: MIW Register Bit Assignments Bit 7
x
Bit 6
x
Bit 5
G5
Bit 4
G4
Bit 3
G3
Bit 2
x
Bit 1
x
Bit 0
x
Figure 18: Multi-input Wakeup (MIW) Block Diagram
Data Bus
5
4
3
WKEN[5:3]
G3 G4 G5
WKEDG[3:5]
10
3 4 5
WKOUT EDGEI
WKPND[3:5]
WKINTEN 10
WKINTEN: Bit 7 of T0CNTR
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9.0 I/O Port
The six I/O pins are bi-directional with the exception of G3 which is always an input with weak pull-up (see Figure 19). The bi-directional I/O pins can be individually configured by software to operate as high-impedance inputs, as inputs with weak pullup, or as push-pull outputs. The operating state is determined by the contents of the corresponding bits in the data and configuration registers. Each bi-directional I/O pin can be used for general purpose I/O, or in some cases, for a specific alternate function determined by the on-chip hardware.
9.1 I/O registers
The I/O pins (G0-G5) have three memory-mapped port registers associated with the I/O circuitry: a port configuration regis-
ter (PORTGC), a port data register (PORTGD), and a port input register (PORTGP). PORTGC is used to configure the pins as inputs or outputs. A pin may be configured as an input by writing a 0 or as an output by writing a 1 to its corresponding PORTGC bit. If a pin is configured as an output, its PORTGD bit represents the state of the pin (1 = logic high, 0 = logic low). If the pin is configured as an input, its PORTGD bit selects whether the pin is a weak pull-up or a high-impedence input. Table 11 provides details of the port configuration options. The port configuration and data registers are both read/writable. Reading PORTGP returns the value of the port pins regardless of how the pins are configured. Since this device supports multi-input wakeup/interrupt, the PORTG inputs have Schmitt triggers.
Figure 19: PORTGD Logic Diagram
Weak Pull-up Control PORTGC PIN GX PORTGD PORTGP
Figure 20: I/O Register bit assignments Bit 7
x
Bit 6
x
Bit 5
G512
Bit 4
G4
Bit 3
G311
Bit 2
G2
Bit 1
G1
Bit 0
G0
Table 11: I/O configuration options Configuration Bit
0 0 1 1
Data Bit
0 1 0 1
Port Pin Configuration
High-impedence input (TRI-STATE input) Input with pull-up (weak one input) Push-pull zero output Push-pull one output
11G3 12G5
is only an input is not available on SOIC-8 package with the reset pin option (ACE8000)
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10.0 In-circuit Programming Specification13,14
The ACEx microcontroller supports in-circuit programming of the internal data EEPROM, code EEPROM, and the initialization registers. An externally controlled four wire interface consisting of a LOAD control pin (G3), a serial data SHIFT-IN input pin (G4), a serial data SHIFT-OUT output pin (G2), and a CLOCK pin (G1) is used to access the on-chip memory locations. Communication between the ACEx microcontroller and the external programmer is made through a 32-bit command and response word described in Table 12. The serial data timing for the four-wire interface is shown in Figure 22 and the programming protocol is shown in Figure 21.
programmer has sent the second rising edge during the LOAD = 0V phase (if the timing specifications in Figure 21 are obeyed). The device will set the R bit of the Status register when the write operation has completed. The external programmer must wait for the SHIFT_OUT pin to go high before bringing the LOAD signal to 5V to initiate a normal command cycle.
10.2 Read Sequence
When reading the device after a write, the external programmer must set the LOAD signal to 5V before it sends the new command word. Next, the 32-bit serial command word (for during a READ) should be shifted into the device using the SHIFT_IN and the CLOCK signals while the data from the previous command is serially shifted out on the SHIFT_OUT pin. After the Read command has been shifted into the device, the external programmer must, once again, set the LOAD signal to 0V and apply two clock pulses as shown in Figure 21 to complete READ cycle. Data from the selected memory location, will be latched into the lower 8 bits of the command word shortly after the second rising edge of the CLOCK signal. Writing a series of bytes to the device is achieved by sending a series of Write command words while observing the devices handshaking requirements. Reading a series of bytes from the device is achieved by sending a series of Read command words with the desired addresses in sequence and reading the following response words to verify the correct address and data contents. The addresses of the data EEPROM and code EEPROM locations are the same as those used in normal operation. Powering down the device will cause the part to exit programming mode.
10.1 Write Sequence
The external programmer brings the ACEx microcontroller into programming mode by applying a super voltage level to the LOAD pin. The external programmer then needs to set the LOAD pin to 5V before shifting in the 32-bit serial command word using the SHIFT_IN and CLOCK signals. By definition, bit 31 of the command word is shifted in first. At the same time, the ACEx microcontroller shifts out the 32-bit serial response to the last command on the SHIFT_OUT pin. It is recommended that the external programmer samples this signal tACCESS (1s) after the rising edge of the CLOCK signal. The serial response word, sent immediately after entering programming mode, contains indeterminate data. After 32 bits have been shifted into the device, the external programmer must set the LOAD signal to 0V, and then apply two clock pulses as shown in Figure 21 to complete program cycle. The SHIFT_OUT pin acts as the handshaking signal between the device and programming hardware once the LOAD signal is brought low. The device sets SHIFT_OUT low by the time the
Table 12: 32-Bit Command and Response Word Bit number Input command word
bits 31 - 30 bit 29 bit 28 bits 27 - 25 bit 24 bits 23 - 18 bits 17 - 8 bits 7 - 0
13 14
Output response word
X
Must be set to 0
Set to 1 to read/write data EEPROM, or the initializa- X tion registers, otherwise 0 Set to 1 to read/write code EEPROM, otherwise 0 Must be set to 0 Set to 1 to read, 0 to write Must be set to 0 Address of the byte to be read or written Data to be programmed or zero if data is to be read X X X X Same as Input command word Programmed data or data read at specified address
Application Note reference: "How to In-Circuit Program the ACEx Family of Microcontrollers." During in-circuit programming, G5 must be either not connected or driven high.
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Figure 21: Programming Protocol13
tSV1 tSV2
A
tload1 tload2 tready tload3 tload4
A
LOAD (G3) CLOCK (G1) SHIFT_IN (G4) SHIFT_OUT (G2) (in write mode) SHIFT_OUT (G2) (in read mode)
enter prog. mode
32 clock pulses
bit 31
bit 30
bit 0
BUSY low by 2nd clock pulse
bit 31 READY
BUSY
A: start of programming cycle
Figure 22: Serial Data Timing
tHI CLOCK (G1) tDIS SHIFT_IN (G4) Valid tDOS SHIFT_OUT (G2) tACCESS Valid tDOH tDIH tLO
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11.0 Brown-out/Low Battery Detect Circuit
The Brown-out Reset (BOR) and Low Battery Detect (LBD) circuits on the ACEx microcontroller have been designed to offer two types of voltage reference comparators. The sections below will describe the functionality of both circuits.
BOR will always be powered-up enabled. Software cannot disable the BOR. The BOR can only be disabled in programming mode by resetting the BOREN bit as long as the global write protect (WDIS) feature is not enabled.
11.2 Low Battery Detect
The Low Battery Detect (LBD) circuit allows software to monitor the VCC level at the lower voltage ranges. LBD has eight software programmable voltage reference threshold levels ranging from 2.0V (Bat_tri[2:0] set to zero) to 3.6V (Bat_trim[2:0] set to one) that can be changed on the fly. Once VCC falls below the selected threshold, the LBD flag in the LBD control register is set. The LBD flag will hold its value until VCC rises above the threshold. (See Figure 23) The LBD bit is read only. If LBD is 0, it indicates that the VCC level is higher than the selected threshold. If LBD is 1, it indicates that the VCC level is below the selected threshold. The threshold level can be adjusted up to eight levels using the three trim bits (Bat_trim[2:0]) of the LBD control register. The LBD flag does not cause any hardware actions or an interruption of the processor. It is for software monitoring only. The LBD function is disabled during HALT/IDLE mode. After exiting HALT/IDLE, software must wait at lease 10s before reading the LBD bit to ensure that the internal circuit has stabilized.
11.1 Brown Out Reset
The Brown-out Reset (BOR) function is used to hold the device in reset when VCC drops below a fixed threshold. While in reset, the device is held in its initial condition until VCC rises above the threshold value. Shortly after VCC rises above the threshold value, an internal reset sequence is started. After the reset sequence, the core fetches the first instruction and starts normal operation. On the devices, the BOR should be used in situations when VCC rises and falls slowly and in situations when VCC does not fall to zero before rising back to operating range. The BOR can be thought of as a supplement function to the Power-on Reset when VCC does not fall below ~1.5V. The Power-on Reset circuit works best when VCC starts from 0V and rises sharply. So in applications where VCC is not constant, the BOR will give added device stability. The BOR circuit must be enabled through the BOR enable bit (BOREN) in the initialization register. The BOREN bit can only be set while the device is in programming mode. Once set, the
Figure 23: LBD Control Register Definition Bit 7 Bit 6
Bat_trim[2:0]
Bit 5
Bit 4
0
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
LBD
Figure 24: BOR/LBD Block Diagram
Vcc
1.8V 2.2V
0
_
BOR to RESET logic
1 S
+
BLSEL16 Adjust Reference Voltage
_
LBD
+
LBD Control Register
7
6
5
4
3
2
1
0
16
See Figure 13 for information on BLSEL.
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12.0 RESET block
When a RESET sequence is initiated, all I/O registers will be reset setting all I/Os to high-impedence inputs. The system clock is restarted after the required clock start-up delay. A reset is generated by any one of the following three conditions: * Power-on Reset (as described in Section 13.0) * Brown-out Reset (as described in Section 11.1) * Watchdog Reset (as described in Section 7.0) * External Reset15 (as described in Section 13.0)
14.0 CLOCK
The ACEx microcontroller has an on-board oscillator trimmed to a frequency of 2MHz who is divided down by two yielding a 1MHz frequency.(See AC Electrical Characteristics.) Upon power-up, the on-chip oscillator runs continuously unless entering HALT mode or using an external clock source. (See Figure 26.) If required, an external oscillator circuit may be used depending on the states of the CMODE bits of the initialization register. (See Table 13) When the device is driven using an external clock, the clock input to the device (G1/CKI) can range between DC to 4MHz. For external crystal configuration, the output clock (CKO) is on the G0 pin. If an external crystal or RC is used, to yield the corresponding instruction clock the input frequency is internally divided down by four. If the device is configured for an external square clock, it will not be divided.
13.0 Power-On-Reset
The Power-On Reset (POR) circuit is guaranteed to work if the rate of rise of VCC is no slower than 10ms/1volt. The POR circuit was designed to respond to fast low to high transitions between 0V and VCC. The circuit will not work if VCC does not drop to 0V before the next power-up sequence. In applications where 1) the VCC rise is slower than 10ms/1 volt or 2) VCC does not drop to 0v before the next power-up sequence the external reset option should be used. The external reset option provides a way to properly reset the ACEx microcontroller if POR cannot be used in the application. The external reset pin contains an internal pull-up resistor.
Table 13: CMODE[0:1] Bit Definition CMODE[0] CMODE[1]
0 1 1 0 0 1
Clock Type
Internal 1 MHz clock External square clock External RC clock
Figure 25: BOR and POR Circuit Relationship Diagram (see AC Electrical Characteristics)
VCC (Pin 8)
BOR output
VCC 1.75 0 VCC 0 Time BOR Output VCC
A
Reset circuit output
Global Reset to Logic
POR output
5.0V 1.8V 0 VCC POR output 0
VCC
External Reset Pin (14-Pin Only)
B
The Reset circuit will trigger when inputs A or B transition from High to Low. At that time the Global Reset signal will go high which will reset all controller logic. The Global Reset will go high and stay high for around 1s.
(Pin 7)
POR Output Pulse
15Available
as option on SOIC-8 package only, it replaces the port G5
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Figure 26: RC Oscillator Diagrams
CKI (G1)
CKO (G0)
R VCC C
15.0 HALT Mode
The HALT mode is a power saving feature that almost completely shuts down the device for current conservation. The device is placed into HALT mode by setting the HALT enable bit (EHALT) of the HALT register through software using only the "LD M, #" instruction. EHALT is a write only bit and is automatically cleared upon exiting HALT. When entering HALT, the internal oscillator and all the on-chip systems including the LBD and the BOR circuits are shut down. The device can exit HALT mode only by the MIW circuit. Therefore, prior to entering HALT mode, software must configure the MIW circuit accordingly. (See Section 8.0) After a wakeup from HALT, a 64 clock cycle start-up delay is initiated to allow the internal oscillator to stabilize before normal execution resumes. Immediately after exiting HALT, software must clear the Power Mode Clear (PMC) register by only using the "LD M, #" instruction. (See Figure 28)
16.0 IDLE Mode
In addition to the HALT mode power saving feature, the device also supports an IDLE mode operation. The device is placed into IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT register through software using only the "LD M, #" instruction. EIDLE is a write only bit and is automatically cleared upon exiting IDLE. The IDLE mode operation is similar to HALT except the internal oscillator, the Watchdog, and the Timer 0 remain active while the other on-chip systems including the LBD and the BOR circuits are shut down. The device can exit IDLE by a Timer 0 overflow every 8192 cycles or/and by the MIW circuit. If exiting IDLE mode with the MIW, prior to entering, software must configure the MIW circuit accordingly. (See Section 8.0) Once a wake from IDLE mode is triggered, the core will begin normal operation by the next clock cycle. Immediately after exiting IDLE mode, software must clear the Power Mode Clear (PMC) register by using only the "LD M, #" instruction. (See Figure 29)
Figure 27: HALT Register Definition Bit 7
x
Bit 6
x
Bit 5
x
Bit 4
x
Bit 3
x
Bit 2
x
Bit 1
EIDLE
Bit 0
EHALT
Figure 28: Recommended HALT Flow
Normal Mode
Figure 29: Recommended IDLE Flow
Normal Mode
LD HALT, #01h
Timer0 Overflow
LD
HALT, #01H
Multi-Input Wakeup
Halt
Multi-Input Wakeup
IDLE Mode
LD
PMC, #00H
LD PMC, #00h
Resume Normal Mode
Resume Normal Mode
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Ordering Information
Core Type Part Number
ACE8001M8 ACE8001M8X ACE8001MT8 ACE8001MT8X ACE8001EM8 ACE8001EM8X ACE8001EMT8 ACE8001EMT8X ACE8000M8 ACE8000M8X ACE8000EM8 ACE8000EM8X
Max. # Program Operating I/Os Memory Size Voltage Range 6
X X X X X X X X X X X X
012
X X X X X X X X X X X X
1K
X X X X X X X X X X X X
2K
1.8 - 5.5V
2.2 - 5.5V
X X X X X X X X X X X X
Tape 0 to -40 to -40 to 8-pin 8-pin and 70C +85C +125C SOIC TSSOP Reel
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Temperature Range
Package
28 ACE8001 Product Family Rev. B.2
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197 (4.800 - 5.004)
8765
0.228 - 0.244 (5.791 - 6.198)
1234
Lead #1 IDENT 0.150 - 0.157 (3.810 - 3.988) 8 Max, Typ. All leads 0.004 (0.102) All lead tips
0.010 - 0.020 x 45 (0.254 - 0.508)
0.053 - 0.069 (1.346 - 1.753)
0.004 - 0.010 (0.102 - 0.254) Seating Plane
0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads
0.016 - 0.050 (0.406 - 1.270) Typ. All Leads
0.014 (0.356) 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508)
Molded Small Out-Line Package (M8) Order Number ACE8001M8/ACE8001EM8/ACE8000M8/ACE8000EM8 Package Number M08A
29 ACE8001 Product Family Rev. B.2
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122 (2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ 0.169 - 0.177 (4.30 - 4.50) (1.78) Typ (0.42) Typ (0.65) Typ
0.246 - 0.256 (6.25 - 6.5)
0.123 - 0.128 (3.13 - 3.30)
1
4
Pin #1 IDENT
Land pattern recommendation
0.0433 Max (1.1) 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) Typ.
See detail A
0.0035 - 0.0079
0.0075 - 0.0118 (0.19 - 0.30)
0-8
Gage plane
DETAIL A Typ. Scale: 40X
0.020 - 0.028 (0.50 - 0.70) Seating plane
0.0075 - 0.0098 (0.19 - 0.25)
Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP (MT8) Order Number ACE8001MT8/ACE8001EMT8 Package Number MTC08
30 ACE8001 Product Family Rev. B.2
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ACE8001 Product Family Arithmetic Controller Engine (ACExTM) for Low Power Applications
ACEx Development Tools
General Information
Fairchild Semiconductor offers different possibilities to evaluate and emulate software written for ACEx. Simulator: Is a Windows program able to load, assemble, and debug ACEx programs. It is possible to place as many breakpoints as needed, trace the program execution in symbolic format, and program a device with the proper options. The ACEx Simulator is available free-of-charge and can be downloaded from Fairchild's web site at www.fairchildsemi.com/products/micro
ACEx Emulator Kit: Fairchild also offers a low cost real-time incircuit emulator kit that includes: Emulator board Emulator software Assembler and Manuals Power supply DIP14 target cable PC cable The ACEx emulator allows for debugging the program code in a symbolic format. It is possible to place one breakpoint and watch various data locations. It also has built-in programming capability. Prototype Board Kits: Fairchild offer two solutions for the simplification of the breadboard operation so that ACEx Applications can be quickly tested. 1) ACEDEMO is can be used for general purpose applications 2) ACETXRX for transmitting / receiving (RF, IR, RS232, RS485) applications. ACEDEMO has 8 switches, 8 LEDs, RS232 voltage translator, buzzer, and a lamp with a small breadboard area.
Ordering P/Ns
Programming Adapters: DIP8 - ACEADAPTN DIP14 - ACEADAPTN14 TSSOP8 - ACEADAPTMT8 SO8 - ACEADAPTM8 SO14 - ACEADAPTM Emulator Kit: ACEICE (110Vac) ACEICEEU (220Vac) Prototype Boards: ACEDEMO ACETXRX (315MHz) ACETXRXEU (433MHz)
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
31 ACE8001 Product Family Rev. B.2
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